1. Field of the Invention
The present invention relates to fractional-N (fractional Number) phase-locked loop (PLL) circuits (hereinafter referred to simply as PLL circuits) that create multiple signals each with a different frequency. The present invention also relates to frequency division methods.
2. Description of the Related Art
It is desired of PLL circuits employed in recent mobile communication devices to quickly switch the frequency of an output signal to a desired frequency so that the mobile communication devices are used with more convenience.
FIG. 1 is a diagram showing a structure of a conventional PLL circuit. As shown in FIG. 1, the PLL circuit includes an oscillator 1, a prescaler 2, a shift register 3, a reference divider 4, a swallow counter 5, a main counter 6, an accumulator 7, a cancellation signal control circuit 8, a phase comparator 9, a charge pump 10, a low-pass filter (LPF) 11, and a voltage-controlled oscillator (VCO) 12.
The reference divider 4 is connected to the oscillator 1 and the shift register 3, and the accumulator 7 is connected to the shift register 3. The cancellation signal control circuit 8 is connected to the accumulator 7, and the phase comparator 9 is connected to the reference divider 4 and the main counter 6.
The charge pump 10 is connected to the phase comparator 9 and the cancellation signal control circuit 8, and the LPF 11 is connected to the charge pump 10. The VCO 12 is connected to the LPF 11. The prescaler 2 is connected to the VCO 12, the swallow counter 5, and the main counter 6. The swallow counter 5 is connected to the prescaler 2, the shift register 3, and the accumulator 7. The main counter 6 is connected to the prescaler 2 and the shift register 3.
FIG. 2 is a circuit diagram showing a structure of the phase comparator 9. As shown in FIG. 2, the phase comparator 9 includes inverting circuits 41 through 63 and NAND circuits 81 through 98, and outputs pulse signals "PHgr"P and "PHgr"R on the basis of a phase difference between a supplied reference signal fr and comparison frequency signal fp.
In the PLL circuit of the above-described structure, the oscillator 1 supplies a reference clock signal CK with the natural frequency of a crystal oscillator to the reference divider 4. The reference divider 4, which is formed of a counter circuit, frequency-divides the reference clock signal CK by a division ratio set by data supplied from the shift register 3. Then, the reference divider 4 supplies the reference signal fr generated by the division to the phase comparator 9.
The main counter 6 supplies the comparison frequency signal fp to the phase comparator 9, which outputs to the charge pump 10 the pulse signals "PHgr"P and "PHgr"R on the basis of the phase difference between the reference signal fr and the comparison frequency signal fp.
The charge pump 10 generates an output signal VOUT on the basis of the pulse signals "PHgr"P and "PHgr"R supplied from the phase comparator 9, and supplies the output signal VOUT to the LPF 11. The LPF 11 smoothes the supplied output signal VOUT by removing high-frequency components therefrom to generate an output signal DOUT. The LPF 11 supplies the output signal DOUT to the VCO 12.
The VCO 12 outputs a signal fvco with a frequency corresponding to the voltage value of the output signal DOUT supplied from the LPF 11, and outputs the signal fvco to the prescaler 2.
The prescaler 2 frequency-divides the input signal fvco by M or M+1 (M: natural number) to generate a signal POUT, and supplies the signal POUT to the main counter 6 and the swallow counter 5. The swallow counter 5 frequency-divides the signal POUT supplied from the prescaler 2 by N, and, if supplied with an overflow signal OVF from the accumulator 7, frequency-divides the signal POUT by N+1 for a given period of time (N: natural number). The prescaler 2 sets the division ratio to M or M+1 depending on a signal MD supplied from the swallow counter 5 and the main counter 6.
The above-described PLL circuit shown in FIG. 1 employs a fractional division setting method to enable fast phase lock, thus including the swallow counter 5 and the main counter 6. In the above-described PLL circuit, a fraction F is supplied to the shift register 3, which supplies a modulus QM for determining phase comparison timing in the phase comparator 9 and the fraction F to the accumulator 7.
The accumulator 7 subtracts the fraction F from the modulus QM at every phase comparison timing in the phase comparator 9, and supplies the overflow signal OVF to the swallow counter 5 when the subtraction result becomes zero.
Thus, in the PLL circuit of FIG. 1 functioning as a fractional-N synthesizer, the division ratio varies with time. Therefore, even after a frequency lock, the phase comparator 9 outputs the pulse signals "PHgr"P and "PHgr"R based on the phase difference to the charge pump 10, which outputs the signal VOUT (a jitter) based on the supplied pulse signals "PHgr"P and "PHgr"R to the LPF 11.
The LPF 11 outputs the signal DOUT, and the VCO 12 performs frequency modulation based on the signal DOUT. Therefore, the output spectrum of the VCO 12 includes an spurious output with a frequency that is a multiple of the frequency of the signal fvco which multiple is an integral multiple of a channel step (the fraction F).
In order to reduce the spurious output resulting from fluctuations in the signal VOUT output from the charge pump 10, the PLL circuit of FIG. 1 includes the accumulator 7 and the cancellation signal control circuit 8.
The cancellation signal control circuit 8, based on a signal ACMD supplied from the accumulator 7, generates a signal SPC having a pulse width proportional to the fluctuation width (a jitter width) of the signal VOUT and supplies the signal SPC to the charge pump 10, thereby controlling the fluctuations in the signal VOUT output from the charge pump 10 to reduce the spurious output.
However, in the conventional PLL circuit of FIG. 1, it is necessary for the cancellation signal control circuit 8 to supply the signal SPC to the charge pump 10 with good accuracy in supply timing so as to effectively cancel spurious noise included in the jitter output of the charge pump 10. This makes timing control in the cancellation signal control circuit 8 difficult and causes the cancellation signal control circuit 8 to be large in size.
It is a general object of the present invention to provide a PLL circuit and a frequency division method in which the above-described disadvantages are eliminated.
A more specific object of the present invention is to provide a simple PLL circuit for reducing spurious noise included in an oscillation output and a frequency division method by means of the simple PLL circuit.
The above objects of the present invention are achieved by a phase-locked loop (PLL) circuit performing a fractional division which circuit includes a phase comparator circuit comparing phases of two signals and outputting first and second phase difference signals based on a phase difference between the two signals, a phase difference signal modulation circuit modulating the second phase difference signals into third phase difference signals, and an oscillator circuit oscillating based on the first and third signals.
The above-described PLL circuit is simply structured and prevents a signal that is a source of spurious noise from being supplied to the oscillator circuit by modulating the second phase difference signals.
The above objects of the present invention are also achieved by a frequency division method including the steps of (a) generating first and second phase difference signals based on a phase difference between two signals, (b) modulating the second phase difference signals into third phase difference signals, and (c) generating a signal with a desired frequency by oscillating based on the first and third phase difference signals.
The above-described method prevents a signal that is a source of spurious noise from being supplied to the oscillator circuit by modulating the second phase difference signals.